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69 lines
3.3 KiB
C++
69 lines
3.3 KiB
C++
/*---------------------------------------------------------*\
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| CorsairDRAMDevices.h |
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| Device list for Corsair DRAM RGB controllers |
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| Adam Honse (CalcProgrammer1) 07 Apr 2026 |
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| This file is part of the OpenRGB project |
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| SPDX-License-Identifier: GPL-2.0-or-later |
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\*---------------------------------------------------------*/
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#pragma once
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#include <string>
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/*---------------------------------------------------------*\
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| Maximum number of PIDs for a given DRAM model |
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\*---------------------------------------------------------*/
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#define CORSAIR_DRAM_MAX_PIDS 6
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/*---------------------------------------------------------*\
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| Corsair DRAM vendor ID |
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\*---------------------------------------------------------*/
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#define CORSAIR_DRAM_VID 0x1B1C
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/*---------------------------------------------------------*\
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| Corsair DRAM product IDs |
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\*---------------------------------------------------------*/
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#define CORSAIR_VENGEANCE_PRO_DDR4_PID_1 0x0100
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#define CORSAIR_VENGEANCE_PRO_DDR4_PID_2 0x0101
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#define CORSAIR_DOMINATOR_PLATINUM_DDR4_PID_1 0x0200
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#define CORSAIR_DOMINATOR_PLATINUM_DDR4_PID_2 0x0201
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#define CORSAIR_VENGEANCE_PRO_SL_DDR4_PID_1 0x0300
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#define CORSAIR_VENGEANCE_PRO_SL_DDR4_PID_2 0x0301
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#define CORSAIR_VENGEANCE_RS_DDR4_PID_1 0x0400
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#define CORSAIR_VENGEANCE_RS_DDR4_PID_2 0x0401
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#define CORSAIR_DOMINATOR_PLATINUM_DDR5_PID_1 0x0600
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#define CORSAIR_DOMINATOR_PLATINUM_DDR5_PID_2 0x0601
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#define CORSAIR_DOMINATOR_TITANIUM_DDR5_PID_1 0x0800
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#define CORSAIR_DOMINATOR_TITANIUM_DDR5_PID_2 0x0801
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#define CORSAIR_DOMINATOR_TITANIUM_DDR5_PID_3 0x0810
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#define CORSAIR_DOMINATOR_TITANIUM_DDR5_PID_4 0x0811
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#define CORSAIR_VENGEANCE_DDR5_PID_1 0x0700
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#define CORSAIR_VENGEANCE_DDR5_PID_2 0x0701
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#define CORSAIR_VENGEANCE_DDR5_PID_3 0x0900
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#define CORSAIR_VENGEANCE_DDR5_PID_4 0x0901
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#define CORSAIR_VENGEANCE_DDR5_PID_5 0x0910
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#define CORSAIR_VENGEANCE_DDR5_PID_6 0x0911
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#define CORSAIR_VENGEANCE_SHUGO_SERIES_DDR5_PID_1 0x0A00
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#define CORSAIR_VENGEANCE_SHUGO_SERIES_DDR5_PID_2 0x0A01
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#define CORSAIR_VENGEANCE_SHUGO_SERIES_DDR5_PID_3 0x0A10
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#define CORSAIR_VENGEANCE_SHUGO_SERIES_DDR5_PID_4 0x0A11
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#define CORSAIR_VENGEANCE_RS_DDR5_PID_1 0x0B00
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#define CORSAIR_VENGEANCE_RS_DDR5_PID_2 0x0B01
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typedef struct
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{
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std::string name;
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unsigned short pids[CORSAIR_DRAM_MAX_PIDS];
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unsigned int led_count;
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bool reverse;
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} corsair_dram_device;
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/*-----------------------------------------------------*\
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| These constant values are defined in RazerDevices.cpp |
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\*-----------------------------------------------------*/
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extern const unsigned int CORSAIR_DRAM_NUM_DEVICES;
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extern const corsair_dram_device** corsair_dram_device_list;
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